[1.1.x] Assorted fixes and improvements (#10914)
Co-Authored-By: ejtagle
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@@ -52,6 +52,10 @@
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#define CRITICAL_SECTION_END SREG = _sreg;
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#endif
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#define ISRS_ENABLED() TEST(SREG, SREG_I)
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#define ENABLE_ISRS() sei()
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#define DISABLE_ISRS() cli()
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// --------------------------------------------------------------------------
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// Types
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// --------------------------------------------------------------------------
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@@ -148,7 +152,6 @@ void TIMER1_COMPA_vect (void) { \
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A("lds r16, %[timsk1]") /* 2 Load into R0 the stepper timer Interrupt mask register [TIMSK1] */ \
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A("andi r16,~%[msk1]") /* 1 Disable the stepper ISR */ \
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A("sts %[timsk1], r16") /* 2 And set the new value */ \
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A("sei") /* 1 Enable global interrupts - stepper and temperature ISRs are disabled, so no risk of reentry or being preempted by the temperature ISR */ \
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A("push r16") /* 2 Save TIMSK1 into stack */ \
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A("in r16, 0x3B") /* 1 Get RAMPZ register */ \
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A("push r16") /* 2 Save RAMPZ into stack */ \
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@@ -258,7 +261,7 @@ void TIMER0_COMPB_vect (void) { \
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A("out 0x3B, r16") /* 1 Restore RAMPZ register to its original value */ \
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A("pop r16") /* 2 Get the original TIMSK0 value but with temperature ISR disabled */ \
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A("ori r16,%[msk0]") /* 1 Enable temperature ISR */ \
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A("cli") /* 1 Disable global interrupts - We must do this, as we will reenable the temperature ISR, and we don´t want to reenter this handler until the current one is done */ \
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A("cli") /* 1 Disable global interrupts - We must do this, as we will reenable the temperature ISR, and we don't want to reenter this handler until the current one is done */ \
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A("sts %[timsk0], r16") /* 2 And restore the old value */ \
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A("pop r16") /* 2 Get the old SREG */ \
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A("out __SREG__, r16") /* 1 And restore the SREG value */ \
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